1. Field of the Invention
The present invention relates to a synchronous semiconductor memory device which strobes external signals including an external control signal, an address signal, write data and the like in synchronization with a clock signal formed of a series of pulse trains, and more particularly, it relates to a structure for refreshing data which are held in memory cells. More specifically, the present invention relates to a structure for enabling testing of a refresh counter which generates refresh addresses for specifying memory cells to be refreshed.
2. Description of the Background Art
The operating speed of a microprocessor (MPU) has been increasingly faster in recent years. On the other hand, a dynamic random access memory (hereinafter referred to as DRAM) which is employed as a main memory cannot follow the MPU in operating speed although its operation has also been speeded up. Thus, it is frequently pointed out that access and cycle times of such a DRAM bottleneck the operation of the overall system, to deteriorate its performance.
In order to improve performance of such a system, frequently employed is a technique of arranging a high-speed memory called a cache memory, which is formed by a high-speed static random access memory (hereinafter referred to as SRAM) between a DRAM and an MPU. This high-speed cache memory is adapted to store frequently-used data, and to be accessed when the cache stores data required by the MPU. The DRAM is accessed only when the cache memory stores no data required by the MPU. Due to the high-speed cache memory storing frequently-used data, it is possible to extremely reduce frequency of access to the DRAM, thereby eliminating influences by the access and cycle times of the DRAM and improving performance of the system.
However, the SRAM is so high-priced as compared with the DRAM that the method employing a cache memory is unsuitable for a relatively low-priced device such as a personal computer. Thus, improvement has been looked for in performance of such a system with a low-priced DRAM.
JEDEC (Joint Electron Device Engineering Council) of the U.S.A. employs a synchronous DRAM (hereinafter referred to as SDRAM) which operates in synchronization with a clock signal as a main memory for a high-speed MPU, and is now in operation for standardizing the specification of the SDRAM. While the standard specification is not yet clarified in detail, the following structure is proposed at present:
(1) The SDRAM is synchronized with a clock signal having a cycle of 10 to 15 ns (nanoseconds).
(2) The first data is randomly accessed with 4 to 6 clocks after a row address signal is inputted. Thereafter data of continuous addresses can be accessed every clock.
(3) Circuits provided in a chip are pipeline-driven while serial input/output buffers are provided in a data input/output part to reduce an access time.
(4) A refresh operation is executed by supplying an automatic refresh command from the exterior.
However, the aforementioned structure is a mere proposal, and no means for implementing this structure is described specifically.
In the aforementioned standard specification, the refresh operation is executed along an automatic refresh command. In relation to such an automatic refresh operation, the following proposal is further made in the standard specification of JEDEC:
(1) The refresh operation is completed after a lapse of a prescribed time upon supply of an automatic refresh command, so that an array including the refreshed memory cells returns to a precharged state.
(2) When two banks are included, these banks are alternately refreshed.
No structure for such a refresh operation is defined in detail. While the refresh operation is automatically executed in the interior by a refresh command, a refresh address counter is required for generating refresh addresses for specifying memory cells to be refreshed, in order to carry out this refresh operation.
In order to periodically refresh memory cells for correctly holding data, such a refresh address counter must normally operate to successively generate refresh addresses. In order to guarantee a normal operation of the refresh address counter, i.e., periodic and cyclic generation of refresh addresses, a test mode is required for checking whether or not the refresh address counter normally operates. However, the standard specification of JEDEC defines no such functional test mode for the refresh address counter.